Initial Exercise: ALU

Let's start with some initial exercises!

1. Complete these two HDLBits exercises, if you have not already

Always case - HDLBitshdlbits.01xz.net

Module add - HDLBitshdlbits.01xz.net

1. Read these ChipVerify pages (it will be helpful for the design!)

Verilog case statementChipVerify

Verilog 4 to 1 Multiplexer/MuxChipVerify

ALU

The ALU, or the arithmetic logic unit, is one of the core components of any processor design. It has 3 simple inputs:

• a: operand 1, 32 bits wide

• b: operand 2. 32 bits wide,

• ALUSel: selector signal, 4 bits wide

There's also one output:

• out output, 32 bits wide

At a high level, what the ALU does is based on the ALUSel signal, it will choose the proper operation to perform on the operands a and b. Our design follows the RV32 specification and should support the same operations, listed below.

Some helpful links:

RISC-V Green Card

https://inst.eecs.berkeley.edu/~cs61c/su22/pdfs/resources/reference-card.pdfinst.eecs.berkeley.edu

Signed vs unsigned representations

Signed Binary Numbers - Electronics-LabElectronics-Lab

Here's a quick table what some of the ALUSel do. For the sake of this assignment, just do the ones that are listed here. The - incidates operations that we will not support at the moment.

ALUSel	Operation	Explanation
0	ADD	Adds the operands
1	SLL	logical left shifts a by b
2	SLT	Signed less than comparison
3	SLTU	Unsigned less than
4	XOR	XORs the operands
5	SRL	logical right shift
6	OR	logical OR
7	AND	logical AND
8	-	-
9	-	-
10	-	-
11	-	-
12	SUB	subtract the operands
13	SRA	arithmetic right shift
14
15	BSEL	set the result to b

Your task: Please write a Verilog module that accomplishes the above operations. These actions should be performed irrespective of clock.

You may choose to write this in either EDAPlayground or the editor in HDLBits, though the EDA Playground editor is much more robust. We also expect you to be able to test this through writing a testbench.

Testing the ALU

When testing Verilog, you typically write something called a testbench. Testbenches simulate the Verilog code that you wrote and checks if certain waveforms are what you expect at each clock tick. Here are some links to read about this:

Verilog Testbench SimulationChipVerify

Verilog TestbenchChipVerify

Your next task is to create a testbench for the ALU you just made. Make sure it tests all the possible cases in the module!