Initial Exercise: ALU
Let's start with some initial exercises!
Complete these two HDLBits exercises, if you have not already
Read these ChipVerify pages (it will be helpful for the design!)
ALU
The ALU, or the arithmetic logic unit, is one of the core components of any processor design. It has 3 simple inputs:
a: operand 1, 32 bits wideb: operand 2. 32 bits wide,ALUSel: selector signal, 4 bits wide
There's also one output:
outoutput, 32 bits wide
At a high level, what the ALU does is based on the ALUSel signal, it will choose the proper operation to perform on the operands a and b. Our design follows the RV32 specification and should support the same operations, listed below.
Some helpful links:
RISC-V Green Card
Signed vs unsigned representations
Here's a quick table what some of the ALUSel do. For the sake of this assignment, just do the ones that are listed here. The - incidates operations that we will not support at the moment.
| ALUSel | Operation | Explanation |
|---|---|---|
0 | ADD | Adds the operands |
1 | SLL | logical left shifts |
2 | SLT | Signed less than comparison |
3 | SLTU | Unsigned less than |
4 | XOR | XORs the operands |
5 | SRL | logical right shift |
6 | OR | logical OR |
7 | AND | logical AND |
8 | - | - |
9 | - | - |
10 | - | - |
11 | - | - |
12 | SUB | subtract the operands |
13 | SRA | arithmetic right shift |
14 | ||
15 | BSEL | set the result to |
Your task: Please write a Verilog module that accomplishes the above operations. These actions should be performed irrespective of clock.
You may choose to write this in either EDAPlayground or the editor in HDLBits, though the EDA Playground editor is much more robust. We also expect you to be able to test this through writing a testbench.
Testing the ALU
When testing Verilog, you typically write something called a testbench. Testbenches simulate the Verilog code that you wrote and checks if certain waveforms are what you expect at each clock tick. Here are some links to read about this:
Your next task is to create a testbench for the ALU you just made. Make sure it tests all the possible cases in the module!
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